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Range and process compensation for a digital phase locked loop (PLL) or frequency locked loop (FLL) circuit
Range and process compensation for a digital phase locked loop (PLL) or frequency locked loop (FLL) circuit
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机译:数字锁相环(PLL)或锁频环(FLL)电路的范围和过程补偿
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摘要
A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.
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