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METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF
METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF
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机译:金属线连接,可提高RRAM的可靠性,包括同一根导线的半导体布置及其制造
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摘要
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.
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