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Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits
Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits
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机译:用于为多电压域和时钟网格以及集成电路合成基于多角网格的时钟分配网络的方法和计算机可读介质
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摘要
One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slewmax within the voltage domain i exceeds a defined slew threshold; (b) calculating maximum insertion delay values for all cases for each of the voltage domains; (c) if the maximum insertion delay values for all cases are associated with a single voltage domain j: (i) adding a max size buffer to all voltage domains except voltage domain j; and (ii) repeating steps (b) and (c); (d) reducing buffer sizes for each of the voltage domains; (e) recalculating maximum insertion delay values; and (f) adding parallel buffers to a first level of the voltage domain having a highest maximum insertion delay until the calculated skew across the plurality of voltage domains no longer improves.
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机译:本发明的一个方面提供了一种方法,包括:(a)在电压域i之一的第(n-1)级上放置N×N个最大大小的缓冲器,直到在该范围内的最大转换slew max Sub>。电压域i超过规定的压摆阈值; (b)计算每个电压域在所有情况下的最大插入延迟值; (c)如果所有情况下的最大插入延迟值都与单个电压域j相关联:(i)向除电压域j外的所有电压域添加最大大小的缓冲区; (ii)重复步骤(b)和(c); (d)减小每个电压域的缓冲区大小; (e)重新计算最大插入延迟值; (f)向具有最高最大插入延迟的电压域的第一级添加并行缓冲器,直到跨多个电压域的计算出的偏斜不再改善为止。
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