首页> 外国专利> Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain

Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain

机译:具有垂直栅极结构的垂直晶体管,该垂直栅极结构具有顶表面或顶表面,该顶表面或顶表面限定在垂直源极和垂直漏极之间形成的小平面

摘要

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.
机译:提供了包括通过受控的选择性外延生长形成的上覆硅层的凸起结构,以及用于在半导体衬底上形成这种凸起结构的方法。通过在半导体衬底的表面上选择性地生长单晶硅的初始外延层,并在外延层上形成绝缘材料的薄膜来形成结构。选择性地在初始外延生长的晶体层的暴露表面上生长第二外延层,并且在第二外延层上沉积绝缘薄膜。根据需要添加其他外延层,以提供具有所需高度的垂直结构,该垂直结构包括多层单晶硅晶体,每个外延层均具有绝缘的侧壁,最上层的外延层也具有绝缘的顶表面。

著录项

  • 公开/公告号US9685536B2

    专利类型

  • 公开/公告日2017-06-20

    原文格式PDF

  • 申请/专利权人 ER-XUAN PING;JEFFREY A. MCKEE;

    申请/专利号US201213407855

  • 发明设计人 ER-XUAN PING;JEFFREY A. MCKEE;

    申请日2012-02-29

  • 分类号H01L29/78;H01L29/66;H01L29/786;H01L21/02;H01L21/285;H01L27/108;

  • 国家 US

  • 入库时间 2022-08-21 13:44:38

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