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High order hybrid phase locked loop with digital scheme for jitter suppression
High order hybrid phase locked loop with digital scheme for jitter suppression
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机译:具有抑制抖动的数字方案的高阶混合锁相环
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摘要
A method for filtering noise. The method may include obtaining an output signal from a phase locked loop (PLL) device. The method may include determining, using a digital phase detector and the output signal, an amount of PLL error produced by the PLL device. The method may include filtering, using a delay element and a digital filter, a portion of the amount of PLL error from the output signal to produce a filtered signal in response to determining the amount of PLL error produced by the PLL device.
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