SCHEME FOR MASKING OUTPUT OF SCAN CHAINS IN TEST CIRCUIT

摘要

A computer implemented method for masking scan chains in a test circuit of an integrated circuit, the method comprising: generating, by a computer, a test pattern to feed into the test circuit of the integrated circuit; responsive to a condition not being met, generating a mask configured to increase a total number of detectable primary, secondary, and tertiary faults; and responsive to the condition being met, generating a mask configured to protect a primary fault associated with the test pattern.