Scheme for masking output of scan chains in test circuit

摘要

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.