METHOD FOR ACHIEVING HIGHER JITTER TOLERANCE IN A CDR CIRCUIT AND THE CDR CIRCUIT THEREOF

摘要

pAn enhanced jitter tolerant clock and data recovery circuit (CDR) comprises of the blind- oversampling CDR placed in a first order delay locked loop with the data. In the blind oversampling CDR the output clock's position is a function of the two abounding edges of the current data-bit and previous "n" data edges. The information on data crossovers is computed by the blind-oversampling circuit and the input data is delayed to coarsely match the computation of the crossovers over 1 UI in the blind-oversampling circuit. The position of the clock phase approximately in the middle of the two abounding data crossovers for a given bit is computed in the blind-oversampling circuit. The delayed data is resampled by the clock phase determined by the blind-oversampling circuit to position it in the middle of the two data crossovers abounding the data-bit on average with a first order delay locked loop formed with the input data. The CDR tolerates a finite frequency offset without employing a separate loop. The clock and data recovery method enhances the jitter tolerance of the CDR and also acquires lock for a burst mode of the data transfer with limited resolution./p[WO2017141258A1]