The sensor performance and ageing to memories SRAMs and DRAMs.

摘要

This invenu00c7u00c3o refers to a sensor for SRAM and DRAM memories that identifies and signals reductions in performance in the operation of reading and writing in the memory cell, for application as a sensor performance and / or aging in digital circuits developed in nanotecno Logias CMOS. This invenu00c7u00c3o is composed of a transiu00c7u00d5es detector and a pulse detector.The detector can generate a pulse transition for each transition existing in a cu00c9lula bit line of memory. The duration of the impulse is directly proportional to the duration of the time transition of bit line.The pulse detector enables you to generate pulses with duration proportional to the time of transition of a signal which toggles on the bit line; the peak detector detects when the duration allows a pulse generated by the transition detector is large enough to indicate the presence of transiu00c7 5 slow occurring in the line of bit, indicating the eminu00cancia errors of reading or writing in the memory.