首页> 外国专利> 3 -- Metal-Interlayer-Semiconductor Structure on Source/Drain Contact for Low Temperature Fabrication with Monolithic 3D Integration Technology and Manufacturing Method

3 -- Metal-Interlayer-Semiconductor Structure on Source/Drain Contact for Low Temperature Fabrication with Monolithic 3D Integration Technology and Manufacturing Method

机译:3-用于单片3D集成技术的低温制造的源/漏触点上的金属层间半导体结构和制造方法

摘要

The present invention, semiconductor layers, including a dielectric layer formed between the forming the source or drain of the semiconductor element metal layer and the metal layer and the semiconductor layer and the dielectric layer on the semiconductor device, the source or drain forming the ALD (Atomic doedoe doped through Layer Deposition) process method, by controlling the doping density of the dielectric layer to control the number of times of the feed cycle of the ALD process, it is possible to provide a semiconductor device that implements the low contact resistance with only low-temperature processes.
机译:本发明的半导体层,包括形成在形成半导体元件金属层的源极或漏极与金属层之间的介电层和半导体装置上的半导体层与介电层之间的电介质层,形成ALD的源极或漏极(通过层沉积来掺杂原子的掺杂方法),通过控制介电层的掺杂密度以控制ALD工艺的馈电周期的次数,可以提供一种半导体器件,该半导体器件仅实现了低接触电阻低温工艺。

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