首页> 外国专利> METHOD OF IMPROVING CIRCUIT FAULT TOLERANCE AND FAULT TOLERANT CIRCUIT FOR ITS IMPLEMENTATION

METHOD OF IMPROVING CIRCUIT FAULT TOLERANCE AND FAULT TOLERANT CIRCUIT FOR ITS IMPLEMENTATION

机译:改善电路故障容限的方法及其实现的容错电路

摘要

FIELD: physics.;SUBSTANCE: method is implemented by connecting unified elements through switches and reconfiguring the circuit in the event of element failure. The method of improving the fault tolerance is as follows. The circuit is decomposed and a number of nodes are selected. Each node consists of unified elements. One or more redundant backup nodes are added to the circuit, which are used, when the main nodes fail. Switchboards are added to the circuit, which ensure interconnections between the elements in the node and the nodes among themselves. The switchboard contains a table for switching inputs and outputs, a device for receiving and transmitting information, a circuit for comparing the output signals. Elements from one or different nodes are grouped together and connected to the switchboards. The switchboards are connected to each other. During the circuit operation, the switchboard controls the operability of the elements. For this purpose the inputs of the main and several backup elements or nodes, the same signals are fed, and the signals are compared at their outputs. If the signals coincide, then all elements or nodes are operable. If the signals do not coincide, then it is determined, which elements or nodes are inoperable. If a circuit element fails, reconfiguration takes place, when a backup element is connected instead of the main element. When reconfiguring, the communication table changes in the switchboard, to which the failed element is connected. With the switchboard disconnects the inefficient elements or nodes, working backup elements or nodes are connected instead of them. Then the serviceability of the elements of the failed node is controlled, and all the serviceable elements are transferred to the reserve. The claimed method is implemented in the device of a fault tolerant circuit. The fault tolerant circuit is developed on the basis of the switchboard architecture and implements a tree structure, where the branches are formed by mutual connections of the switchboards 4, and the leaves are formed by the main and backup elements connected to the switchboards 1,2,3.;EFFECT: increasing the circuit fault tolerance.;2 cl, 4 dwg
机译:领域:物理学;实体:方法是通过开关连接统一的元素并在元素发生故障时重新配置电路来实现的。改善容错性的方法如下。电路被分解,并选择了许多节点。每个节点由统一元素组成。当主节点发生故障时,将一个或多个冗余备用节点添加到电路中,以供使用。配电盘被添加到电路中,以确保节点中的元素与节点之间的互连。配电盘包含用于切换输入和输出的表格,用于接收和传输信息的设备以及用于比较输出信号的电路。来自一个或不同节点的元素被分组在一起并连接到配电盘。配电盘相互连接。在电路操作期间,配电盘控制元件的可操作性。为此,主要和几个备用元件或节点的输入,相同的信号被馈送,并且信号在它们的输出处进行比较。如果信号一致,则所有元件或节点都可操作。如果信号不一致,则确定哪些元件或节点不可操作。如果电路元件发生故障,则在连接备用元件而不是主元件时会进行重新配置。重新组态时,通讯表将在故障面板所连接的配电盘中更改。使用配电盘断开低效的元素或节点时,将连接工作中的备用元素或节点而不是它们。然后,控制故障节点的元素的可维护性,并将所有可维护的元素转移到备用节点。所要求保护的方法在容错电路的设备中实现。容错电路是在配电盘结构的基础上开发的,并实现了树形结构,其中分支是由配电盘4的相互连接形成的,分支是由连接到配电盘1,2的主,备用元件形成的。 ,3 .;效果:提高电路容错能力;; 2 cl,4 dwg

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号