TRANSCEIVER ARCHITECTURE THAT MAINTAINS LEGACY TIMING BY INSERTING AND REMOVING CYCLIC PREFIX AT LEGACY SAMPLING RATE

摘要

Systems and methods relating to a transceiver architecture that maintains legacy timing by inserting and removing a cyclic prefix at a legacy sampling rate are disclosed. In some embodiments, a system for a receiver comprises an upsampling subsystem, a cyclic prefix removal unit, and a downsampling subsystem. The upsampling subsystem is operable to process a first baseband receive signal that is at a first sampling rate to generate an upsampled baseband receive signal at a second sampling rate that is greater than the first sampling rate. The cyclic prefix removal unit is operable to remove a cyclic prefix from the upsampled baseband receive signal to provide a second baseband receive signal at the second sampling rate. The downsampling subsystem is operable to process the second baseband receive signal to generate a downsampled baseband receive signal at the first sampling rate. In this manner, complexity and power consumption are reduced.