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IMPROVED TRANSISTOR DESIGN USED IN ADVANCED NANOMETER FLASH MEMORY DEVICE

机译:先进的纳米闪存器件中改进的晶体管设计

摘要

PROBLEM TO BE SOLVED: To provide an improved transistor design technique used in advanced nanometer flash memory devices.SOLUTION: In a decoder used for a memory device, a plurality of reception blocks 700, 701-707 configured to receive from bit lines are composed of two types of transistors different in proximity effect and STI effect from each other. In each of PMOS and NMOS transistors, two types of transistors are used for a sense circuit, and thereby performance of an analog circuit is improved.SELECTED DRAWING: Figure 7
机译:解决的问题:提供用于先进的纳米闪存设备的改进的晶体管设计技术。解决方案:在用于存储设备的解码器中,配置为从位线接收的多个接收块700,701-707包括:两种晶体管的邻近效应和STI效应互不相同。在每个PMOS和NMOS晶体管中,两种类型的晶体管都用于检测电路,从而提高了模拟电路的性能。图7

著录项

  • 公开/公告号JP2017224381A

    专利类型

  • 公开/公告日2017-12-21

    原文格式PDF

  • 申请/专利权人 SILICON STORAGE TECHNOLOGY INC;

    申请/专利号JP20170157137

  • 申请日2017-08-16

  • 分类号G11C16/24;G11C16/26;G11C16/28;H01L21/336;H01L29/788;H01L29/792;H01L27/10;H01L27/11526;H01L27/11573;

  • 国家 JP

  • 入库时间 2022-08-21 13:10:19

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