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Partitioning circuit designs for implementation within multi-die integrated circuits
Partitioning circuit designs for implementation within multi-die integrated circuits
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机译:划分电路设计以在多晶粒集成电路中实现
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摘要
Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.
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