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PESSIMISM REDUCTION IN HIERARCHICAL BLOCKAGE AGGRESSORS USING ESTIMATED RESISTOR AND CAPACITOR VALUES
PESSIMISM REDUCTION IN HIERARCHICAL BLOCKAGE AGGRESSORS USING ESTIMATED RESISTOR AND CAPACITOR VALUES
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机译:使用估计的电阻器和电容器值降低分层阻塞聚集器的悲观主义
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摘要
A method, system, and computer product for performing a coupled noise analysis in an integrated circuit (IC) design include copying one or more victim circuit sections of a victim circuit in the IC, generating a blockage circuit section that represents a blockage aggressor circuit in the IC, using the copied one or more victim sections of the victim circuit, determining at least one subcircuit from the blockage circuit section, selecting, for a victim pin on the victim circuit, a power-driven virtual node on the at least one subcircuit, applying a power source to the power-driven virtual node on the at least one subcircuit, calculating a coupled noise at the victim pin contributed by the at least one subcircuit in response to the power source being applied, comparing the coupled noise to a threshold noise level, and altering the IC design when the coupled noise exceeds the threshold noise level.
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