Systems, methods, and apparatuses for implementing testing of a far memory subsystem within two-level memory (2LM) stacked die subsystems

摘要

A stacked semiconductor package includes a functional silicon die, and a test controller having signature accumulation logic embedded therein. A fabric to route transactions is between the test controller and a far memory controller of the functional silicon die. The far memory controller includes a physical memory interface having no physical memory attached. A Two Level Memory (2LM) controller is included having logic to modify received transactions to indicate a cache miss forcing all received transactions to be routed to the far memory controller via the fabric. An auto response mechanism is included to observe the transactions on the fabric and route responses and completions issued in reply to the transactions back to an agent having initiated the transactions.