SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING TESTING OF FAULT REPAIRS TO A THROUGH SILICON VIA (TSV) IN TWO-LEVEL MEMORY (2LM) STACKED DIE SUBSYSTEMS

摘要

Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.