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THERMALLY STABLE CHARGE TRAPPING LAYER FOR USE IN MANUFACTURE OF SEMICONDUCTOR-ON-INSULATOR STRUCTURES
THERMALLY STABLE CHARGE TRAPPING LAYER FOR USE IN MANUFACTURE OF SEMICONDUCTOR-ON-INSULATOR STRUCTURES
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机译:用于绝缘体上绝缘体结构制造的热稳定电荷陷阱层
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摘要
A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.
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