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LIFT OFF PROCESS FOR CHIP SCALE PACKAGE SOLID STATE DEVICES ON ENGINEERED SUBSTRATE

机译:工程基板上芯片规模固态包装设备的提升过程

摘要

A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.
机译:一种处理工程衬底结构的方法,包括提供包括多晶衬底和封装多晶衬底的工程层的工程衬底结构,形成与工程层耦合的牺牲层,将固态器件结构与牺牲层接合,形成一个通过去除固态器件结构的一个或多个部分以暴露牺牲层的一个或多个部分,使蚀刻剂流过一个或多个通道到达固态器件结构的一个或多个暴露部分,从而在固态器件结构中形成一个或多个通道。牺牲层,并通过蚀刻化学品和牺牲层之间的相互作用溶解牺牲层,从而将工程衬底结构与固态器件结构分离。

著录项

  • 公开/公告号US2018261488A1

    专利类型

  • 公开/公告日2018-09-13

    原文格式PDF

  • 申请/专利权人 QROMIS INC.;

    申请/专利号US201815974606

  • 发明设计人 VLADIMIR ODNOBLYUDOV;CEM BASCERI;

    申请日2018-05-08

  • 分类号H01L21/683;H01L33;

  • 国家 US

  • 入库时间 2022-08-21 13:01:53

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