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Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
Apparatus and method for implementing design for testability (DFT) for bitline drivers of memory circuits
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机译:用于实现存储电路的位线驱动器的可测试性(DFT)的设计的设备和方法
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摘要
A first bitline driver includes a multiplexer for outputting data and write mask signals in functional mode, and test vector signal in test mode; a latch to latch the data signal in functional mode and the test vector signal in test mode; a latch to latch the write mask signal in functional mode and the test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell based on the data signal. A second bitline driver includes a latch to latch a data signal in functional mode if a write mask signal is deasserted and to latch a test vector signal in test mode; a latch to latch the test vector signal and provide it to a scan output; and a write circuit for writing data to a memory cell.
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