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LOW RESISTANCE DUAL LINER CONTACTS FOR FIN FIELD-EFFECT TRANSISTORS (FinFETs)
LOW RESISTANCE DUAL LINER CONTACTS FOR FIN FIELD-EFFECT TRANSISTORS (FinFETs)
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机译:鳍式场效应晶体管(FinFET)的低电阻双衬里触点
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摘要
A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first source/drain on the substrate corresponding to the n-type transistor, a second source/drain on the substrate corresponding to the p-type transistor, a first contact trench over the first source/drain and adjacent the first gate structure, a second contact trench over the second source/drain and adjacent the second gate structure, a first liner layer in the first trench positioned at a bottom part of the first trench, a second liner layer in the second trench and on the first liner layer in the first trench, a metallization layer in the first and second trenches on the second liner layer, and a first silicide contact between the first liner layer and the first source/drain and a second silicide contact between the second liner layer and the second source/drain.
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