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Computer implemented system and method for reducing failure in time soft errors of a circuit design
Computer implemented system and method for reducing failure in time soft errors of a circuit design
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机译:用于减少电路设计的时间软错误中的故障的计算机实现的系统和方法
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摘要
A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.
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