Method and device for debugging a MIPS-structure CPU with southbridge and northbridge chipsets

摘要

The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.