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Multi-core CPU system for adjusting L2 cache character, method thereof, and devices having the same
Multi-core CPU system for adjusting L2 cache character, method thereof, and devices having the same
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机译:用于调整二级缓存字符的多核CPU系统,方法及其装置
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摘要
A multi-core CPU system includes a shared L2 cache, an access control logic circuit, a plurality of cores, each core configured to access the shared L2 cache through the access control logic circuit, and a size adjusting circuit configured to adjust a size of the shared L2 cache in response to an indication signal that indicates a number of operation cores among the plurality of cores.
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