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Minimum track standard cell circuits for reduced area

机译:最小轨道标准单元电路以减小面积

摘要

Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits.
机译:提供了用于减小面积的最小轨道标准单元电路。在一个方面,最小轨道标准单元电路采用第一高纵横比电压轨,该电压轨设置在第一半条轨道上并且被配置为向最小轨道标准单元电路提供第一电压(例如,VDD)。第二高纵横比电压轨被布置在基本平行于第一高纵横比电压轨的第二半轨道上。第二高纵横比电压轨被配置为向最小轨道标准单元电路提供小于第一电压(例如,VSS)的第二电压。最小轨道标准单元电路采用布置在第一和第二半轨道之间的多个轨道。可以根据特定因素来限制磁道的数量。与传统的标准单元电路相比,最小化走线可以减小面积。

著录项

  • 公开/公告号US9985014B2

    专利类型

  • 公开/公告日2018-05-29

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号US201615266523

  • 申请日2016-09-15

  • 分类号G06F17/50;H01L27;H01L27/02;H01L29/423;

  • 国家 US

  • 入库时间 2022-08-21 12:56:37

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