首页> 外国专利> VERTICAL STRING OF MEMORY CELLS INDIVIDUALLY COMPRISING A PROGRAMMABLE CHARGE STORAGE TRANSISTOR COMPRISING A CONTROL GATE AND A CHARGE STORAGE STRUCTURE AND METHOD OF FORMING A VERTICAL STRING OF MEMORY CELLS INDIVIDUALLY COMPRISING A PROGRAMMABLE CHARGE STORAGE TRANSISTOR COMPRISING A CONTROL GATE AND A CHARGE STORAGE STRUCTURE

VERTICAL STRING OF MEMORY CELLS INDIVIDUALLY COMPRISING A PROGRAMMABLE CHARGE STORAGE TRANSISTOR COMPRISING A CONTROL GATE AND A CHARGE STORAGE STRUCTURE AND METHOD OF FORMING A VERTICAL STRING OF MEMORY CELLS INDIVIDUALLY COMPRISING A PROGRAMMABLE CHARGE STORAGE TRANSISTOR COMPRISING A CONTROL GATE AND A CHARGE STORAGE STRUCTURE

机译:垂直存储单元的单个存储单元,该存储单元包括一个由控制门和存储存储单元组成的可编程存储晶体管,以及一种垂直存储单元的存储单元,该存储单元的垂直存储单元包括一个由可存储的存储存储单元组成的存储单元

摘要

A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically- alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.
机译:一种形成垂直存储单元串的方法,包括形成包括第一交替层的下部堆叠,该第一交替层包括垂直交替的控制栅材料和绝缘材料。上部叠层形成在下部叠层上方,并且包括第二交替层,该第二交替层包括垂直交替的控制栅极材料和绝缘材料,该绝缘材料具有向上延伸穿过多个第二交替层的上部开口。下部堆叠包括下部开口,该下部开口竖直地延伸穿过多个第一交替层,并且该下部开口通过堵塞材料而被堵塞。上部开口的至少一部分在被闭塞的下部开口上方立起。去除堵塞下部开口的堵塞材料,以形成包括未堵塞的下部开口和上部开口的互连开口。将电荷存储材料沉积到上下堆叠中的每个中的用于垂直串的存储单元的电荷存储结构的互连开口中,然后将隧道绝缘体和沟道材料形成在用于存储单元的互连开口中。每个上下堆栈中的垂直字符串。公开了其他实施例,包括独立于方法的实施例。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号