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III-N SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE SUBSTRATE TAPS

机译:III-N型半导体器件,带有掺杂的掺杂晶体基底的丝锥

摘要

Semiconductor devices including III-N transistors adjacent to III-N substrate taps extending from a group IV heteroepitaxial growth substrate are described. In embodiments, GaN mesas that are to host conductive substrate taps are grown concurrently with GaN mesas that are to host transistors. A GaN mesa for a substrate tap is then selectively doped, for example with a masked implant. An intrinsic GaN mesa for a transistor is then selectively processed, for example to form a transistor channel. Heavily doped semiconductor may then be grown on all GaN mesas and contact metallization landed on the heavily doped semiconductor. Backend interconnect levels may then be successively landed on the substrate tap to maintain an electrical path to the substrate sufficient to mitigate charging-related damage to the transistors during backend processing.
机译:描述了包括与从IV族异质外延生长衬底延伸的III-N衬底抽头相邻的III-N晶体管的半导体器件。在实施例中,要承载导电衬底抽头的GaN台面与要承载晶体管的GaN台面同时生长。然后例如利用掩膜植入物选择性地掺杂用于衬底抽头的GaN台面。然后,选择性地处理晶体管的本征GaN台面,例如形成晶体管沟道。然后,可以在所有GaN台面上生长重掺杂半导体,并在重掺杂半导体上沉积接触金属化层。然后可以将后端互连层连续地降落在衬底抽头上,以维持到衬底的电路径,该电路径足以减轻在后端处理期间对晶体管的充电相关的损坏。

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