III-N SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE SUBSTRATE TAPS
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机译:III-N型半导体器件,带有掺杂的掺杂晶体基底的丝锥
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摘要
Semiconductor devices including III-N transistors adjacent to III-N substrate taps extending from a group IV heteroepitaxial growth substrate are described. In embodiments, GaN mesas that are to host conductive substrate taps are grown concurrently with GaN mesas that are to host transistors. A GaN mesa for a substrate tap is then selectively doped, for example with a masked implant. An intrinsic GaN mesa for a transistor is then selectively processed, for example to form a transistor channel. Heavily doped semiconductor may then be grown on all GaN mesas and contact metallization landed on the heavily doped semiconductor. Backend interconnect levels may then be successively landed on the substrate tap to maintain an electrical path to the substrate sufficient to mitigate charging-related damage to the transistors during backend processing.
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