An approach and resulting structure for integrating an STT-MRAM memory array into a logic processor

摘要

An approach for integrating STT-MRAM memory arrays into a logic processor, and the resulting structure, is described. In an example, a logic processor includes a logic region that includes metal line / via pairs disposed in a dielectric layer disposed over a substrate. The logic processor also includes an STT-MRAM array including a plurality of MTJs. The MTJs are disposed in the dielectric layer.