Reduced STI topography in high-G metal gate transistors by using a mask after deposition of a channel semiconductor alloy

摘要

A method comprising: forming a mask layer (204) on a first active region (202a) and a second active region (202b) of a semiconductor device (200); Forming a first etch mask (205) to cover the second active region (202b) and leave free the first active region (202a); Selectively removing the mask layer (204) from the first active region (202a) using the first etch mask (205); Forming a layer of a semiconductor alloy (208) on the first active region (202a) using the mask layer (204) on the second active region (202b) as a growth mask; Forming a second etch mask (210) such that it covers the first active region (202a) and exposes the second active region (202b) based on a lithography step in which a lithography mask is used that is inverse with respect to a lithography mask for the production of the first etching mask (205); Removing the mask layer (204) from the second active region using the second etch mask (210); Forming a first gate electrode structure of a first transistor over the first active region (202a) and a second gate electrode structure of a second transistor over the second active region (202b), the first and second gate electrode structures comprising a metal-containing gate electrode material and a gate insulation layer having a large-dielectric material have ε; and forming drain and source regions in the first (202a) and second (202b) active regions after formation of the first and second gate electrode structures.