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INTEGRATED CIRCUIT SHAPED WITH A STACK OF TWO CHIPS CONNECTED IN SERIES

机译:集成电路,具有堆叠的两个芯片系列

摘要

An integrated circuit (100) includes a first chip (30) having a depletion mode high voltage transistor and a second chip (40) having an enhancement mode device, the first (30) and second (40) chips having on their front face respectively first and second contact pads gate (31,41), source (32,42) and drain (33,43). The integrated circuit (100) is remarkable in that: • The first chip (30) and the second chip (40) are assembled together at their respective front faces (34,44) and form a stack (50), the surface of the first chip (30) being greater than that of the second chip (40) so that a peripheral portion of the front face (34) of the first chip (30) is not masked by the second chip (40), • the first chip (30) comprises at least one additional contact pad (331) disposed on its front face (34), electrically isolated from the high voltage transistor in depletion mode, and in contact with the second stud gate contact (41), • The first gate contact pad (31) is in contact with the second source contact pad (42) and / or the first source pad (32) is in contact with the second drain contact pad (43), • the first gate contact pad (31) and the contact pad ad In the peripheral portion of the first chip (30), at least part of the distribution (331) extends.
机译:集成电路(100)包括具有耗尽型高压晶体管的第一芯片(30)和具有增强型器件的第二芯片(40),第一(30)和第二(40)芯片的正面分别第一和第二接触垫栅极(31,41),源极(32,42)和漏极(33,43)。集成电路(100)的显着之处在于:•第一芯片(30)和第二芯片(40)在其各自的正面(34,44)组装在一起并形成堆栈(50),第一芯片(30)大于第二芯片(40),从而第一芯片(30)的正面(34)的外围部分不会被第二芯片(40)遮盖;•第一芯片(30)包括至少一个附加的接触垫(331),位于其正面(34)上,以耗尽模式与高压晶体管电隔离,并与第二柱形栅极触点(41)接触,•第一栅极接触垫(31)与第二源极接触垫(42)和/或第一源极垫(32)与第二漏极接触垫(43),•第一栅极接触垫(31)和在第一芯片(30)的外围部分中,分布(331)的至少一部分延伸。

著录项

  • 公开/公告号FR3059155A1

    专利类型

  • 公开/公告日2018-05-25

    原文格式PDF

  • 申请/专利权人 EXAGAN;

    申请/专利号FR20160061379

  • 申请日2016-11-23

  • 分类号H01L27/085;H01L23/48;H01L25/07;H01L29/778;

  • 国家 FR

  • 入库时间 2022-08-21 12:32:54

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