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INTEGRATED CIRCUIT SHAPED WITH A STACK OF TWO CHIPS CONNECTED IN SERIES

机译:集成电路,具有堆叠的两个芯片系列

摘要

An integrated circuit includes a first chip including a high-voltage depletion-mode transistor and a second chip including an enhancement-mode device. The chips have first and second gate contact pads, first and second source contact pads and first and second drain contact pads, respectively, on their front sides. Chips are joined together via their front sides, and the area of the first chip is larger than that of the second chip. The first chip includes an additional contact pad on its front side that is electrically insulated from the high-voltage depletion-mode transistor and that contacts the second gate contact pad. The first gate contact pad contacts the second source contact pad and/or the first source contact pad contacts the second drain contact pad. The first gate contact pad and the additional contact pad extend at least partially into a peripheral portion of the first chip.
机译:一种集成电路,包括:第一芯片,其包括高压耗尽型晶体管;以及第二芯片,其包括增强型器件。芯片在其正面分别具有第一和第二栅极接触垫,第一和第二源极接触垫以及第一和第二漏极接触垫。芯片通过它们的前侧结合在一起,并且第一芯片的面积大于第二芯片的面积。第一芯片在其前侧上包括附加的接触垫,该接触垫与高压耗尽型晶体管电绝缘并且接触第二栅极接触垫。第一栅极接触垫接触第二源极接触垫和/或第一源极接触垫接触第二漏极接触垫。第一栅极接触垫和附加接触垫至少部分地延伸到第一芯片的外围部分中。

著录项

  • 公开/公告号FR3059155B1

    专利类型

  • 公开/公告日2018-11-16

    原文格式PDF

  • 申请/专利权人 EXAGAN;

    申请/专利号FR20160061379

  • 申请日2016-11-23

  • 分类号H01L27/085;H01L29/778;H01L25/07;H01L23/48;

  • 国家 FR

  • 入库时间 2022-08-21 11:43:56

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