Address generators for verifying integrated circuit hardware designs for cache memory

摘要

One or more address generators 902 are used to verify an integrated circuit hardware design 906 for an n-way set associative cache (figure 4). The address generator creates, from a reverse hashing algorithm matching the hashing algorithm used by the cache, a list of cache set addresses (504 figure 6) that comprises one or more addresses of the main memory (604 figure 6) corresponding to each of one or more target sets of the n-way set associative cache (602 figure 6). The address generator 902 receives requests for addresses of main memory from a driver 904 to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache 906. In response to receiving a request (ADDRESS REQUEST) the address generator provides an address from the list of cache set addresses. In an embodiment a system is defined to execute the verification comprising one or more processor and memory comprising computer executable instructions, an address generator, an address generator module. A method of verification is also included.