首页>
外国专利>
Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
展开▼
机译:地址生成器,用于验证高速缓存的集成电路硬件设计
展开▼
页面导航
摘要
著录项
相似文献
摘要
Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
展开▼