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Clock recovery circuit for a receiver using a decision-feedback equalizer
Clock recovery circuit for a receiver using a decision-feedback equalizer
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机译:使用判决反馈均衡器的接收机时钟恢复电路
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摘要
A signal equalization method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more than one fourth of a data rate for the transmitted data; generating by the phase-error detector a phase-error level based on the detected phase errors; and recovering, by a clock-recovery circuit for the DFE and the phase-error detector, a clock signal associated with the transmitted data based on the phase error level.
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