A 10 Gb/s receiver with equalizer and clock and data recovery circuit.

摘要

Wireline communications systems continue to evolve to support ever-higher speeds. At multi-Gb/s data rates, the transmission medium, such as a backplane or cable, severely limits the signal bandwidth. The high frequency roll-off of the channel, as well as its nonlinear phase response, introduces intersymbol interference (ISI). The signal quality also degrades as a result of wave reflections from channel discontinuities such as connectors, backplane vias, and so on. Noise and crosstalk from the adjacent channels further degrades the signal integrity.;This work describes a 10Gb/s non-return-to-zero (NRZ) receiver for high-speed serial communications. We first present a 10Gb/s equalizer circuit, which consists of a programmable linear feedforward equalizer (FFE) in cascade with a decision-feedback equalizer (DFE). This combination of a nonlinear DFE with a linear FFE decreases the ISI without excessively boosting the high frequency noise and crosstalk. In the second part of this dissertation, we present a fully-integrated dock and data recovery circuit (CDR) that employs a new glitch-free phase and frequency detector (PFD). The glitch-free PFD architecture minimizes CDR jitter generation and maximizes its jitter tolerance. The CDR has two independent charge-pump circuits for each of the phase detector and frequency detector signals. This architecture reduces CDR jitter while simultaneously achieving fast frequency acquisition. The prototype is fabricated in a 0.25um SiGe BiCMOS process with a 50GHz peak ft. The equalizer provides up to 20dB of high-frequency boost at 5GHz. The recovered clock has a 1.1ps rms jitter and the loop has a minimum jitter tolerance of 0.4UI.