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DFT APPROACH TO ENABLE FASTER SCAN CHAIN DIAGNOSIS
DFT APPROACH TO ENABLE FASTER SCAN CHAIN DIAGNOSIS
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机译:DFT方法可实现更快的扫描链诊断
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摘要
A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.
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