首页> 外国专利> HIGH-RELIABILITY ONE-TIME PROGRAMMABLE MEMORY ADOPTING SERIES HIGH VOLTAGE PARTITION

HIGH-RELIABILITY ONE-TIME PROGRAMMABLE MEMORY ADOPTING SERIES HIGH VOLTAGE PARTITION

机译:高可靠性一次性可编程存储器系列高电压分区

摘要

A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube (1), a second MOS tube (2) and an anti-fuse element (4), wherein a gate end of the first MOS tube (1) is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube (2) and a voltage limiting device (3), and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube (2) is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device (3) and the second connecting end of the first MOS tube (1). The high-reliability one-time programmable memory adopting series high voltage partition further comprises the voltage limiting device (3), which comprises a control end and two connecting ends, wherein the control end is connected to a control signal line (WB), one connecting end is connected to a first connecting line (WP) through the anti-fuse device (4), and the other connecting end is connected to the gate end of the second MOS tube (2). In this way, the problem in the prior art that a device of a critical path is damaged and degraded due to high voltage pulse is solved, and possible hidden leakage troubles are avoided.
机译:采用串联高压分区的高可靠性一次性可编程存储器,涉及集成电路技术,包括第一MOS管(1),第二MOS管(2)和反熔丝元件(4),其中第一MOS管(1)的栅极端连接到第二连接线(WS),第一MOS管的第一连接端与第二MOS管(2)的栅极端和限压装置( 3),第一MOS管的第二连接端与第三连接线(BL)连接;第二MOS管(2)的第一连接端连接到第四连接线(BR),第二MOS管的第二连接端连接到第三连接线(BL),第二栅极的栅极MOS管连接到限压装置(3)和第一MOS管(1)的第二连接端。采用串联高压分区的高可靠性一次性可编程存储器还包括限压装置(3),限压装置(3)包括控制端和两个连接端,控制端与控制信号线(WB)相连,一个连接端通过反熔丝装置(4)连接到第一连接线(WP),另一连接端连接到第二MOS管(2)的栅极端。这样,解决了现有技术中由于高压脉冲而导致关键路径的器件损坏和退化的问题,避免了潜在的泄漏隐患。

著录项

  • 公开/公告号EP3413315A1

    专利类型

  • 公开/公告日2018-12-12

    原文格式PDF

  • 申请/专利权人 SICHUAN KILOWAY ELECTRONICS INC.;

    申请/专利号EP20160888851

  • 发明设计人 PENG JACK Z.;MAO JUNHUA;LIAO XUYANG;

    申请日2016-02-18

  • 分类号G11C17/16;G11C17/08;G11C17/12;G11C17/14;

  • 国家 EP

  • 入库时间 2022-08-21 12:27:16

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