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Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)
Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)
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机译:在集成电路(IC)的互连结构中形成自对准垂直互连访问(VIA)
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摘要
Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.
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