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Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify
Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify
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机译:编程验证后,通过修改两层堆栈中接口的字线电压来减少编程干扰
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摘要
A memory device and associated techniques for reducing program disturb of memory cells which are formed in a two-tier stack with an increased distance between memory cells at an interface between the tiers. After a verify test in a program loop, a different timing is used for decreasing the word line voltages of the interface memory cells compared to the remaining memory cells. In one aspect, the start of the decrease of the word line voltages of the interface memory cells is delayed. In another aspect, the word line voltages of the interface memory cells is decreased to an intermediate level and held for a time period before being decreased further. In another aspect, the word line voltages of the interface memory cells are decreased at a lower rate.
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