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Hierarchical computations on sparse matrix rows via a memristor array
Hierarchical computations on sparse matrix rows via a memristor array
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机译:通过忆阻器数组对稀疏矩阵行进行分层计算
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摘要
Hierarchical computation on sparse matrix rows is disclosed. One example is a circuit including a sparse row processor to identify a sparse row of a matrix, where the identified row has a number of non-zero entries less than a threshold, associate a sub-vector of an input vector with a sub-row of the identified row, where the sub-row comprises the non-zero entries of the identified row, and where entries in the sub-vector correspond to the non-zero entries in the identified row in a multiplication operation, and map entries in the matrix to an engine formed from a memristor array. A stream buffer queues sub-vectors based on a position of associated sub-rows of identified sparse rows. The engine computes analog multiplication results between sub-rows and their associated sub-vectors, where each column of the array is configured to hierarchically compute multiple multiplication results based on the queue.
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