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Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits

机译:可缩放电路的已加工晶片,其制造方法以及包括缩放电路的装置

摘要

A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
机译:经处理的半导体晶片具有限定电路的分层元件和围绕每个单独电路的双密封环。分层元件还限定了包围至少两个电路的另一个双密封环。处理后的半导体晶片可以具有附加的分层元件,该附加的分层元件延伸围绕单个电路的每个双密封环,或者可以延伸另一个双密封环。一种制造这种处理过的半导体晶片的方法。一种包括两个这样的电路的设备。

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