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Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits
Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits
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机译:可缩放电路的已加工晶片,其制造方法以及包括缩放电路的装置
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摘要
A processed semiconductor wafer has layered elements that define electrical circuits and a double-seal ring surrounding each individual electrical circuit. The layered elements further define another double-seal ring that surrounds at least two electrical circuits. The processed semiconductor wafer can have additional layered elements that extend each of the double-seal rings that surround individual circuits or, that can extend the other double-seal ring. A method of fabricating such a processed semiconductor wafer. A device comprising two such electrical circuits.
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