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MODELING 3D PHYSICAL CONNECTIVITY INTO PLANAR 2D DOMAIN TO IDENTIFY VIA REDUNDANCY
MODELING 3D PHYSICAL CONNECTIVITY INTO PLANAR 2D DOMAIN TO IDENTIFY VIA REDUNDANCY
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机译:将3D物理连通性建模到平面2D域中以通过冗余识别
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摘要
An integrated circuit (IC) design is received. The IC design has devices on different layers electrically connected to each other by conductive vias extending between the different layers. Relative locations of the vias, and of conductive components of the devices within adjacent layers of the different layers, are identified. The conductive components that overlap redundant vias are also identified. This allows 2D via checker data, that is a combination of the 3D adjacent layers, to be generated. The 2D via checker data includes rectangular geometric shapes that represent each instance of the conductive components overlapping redundant vias. Thus, the 2D via checker data is output, and lack of rectangular geometric shapes in the 2D via checker data provides data of locations in the IC design that fail to have redundant vias.
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机译:接收到集成电路(IC)设计。 IC设计在不同层上的器件通过在不同层之间延伸的导电通孔彼此电连接。确定通孔的相对位置以及在不同层的相邻层内的器件的导电部件的相对位置。还标识了与冗余通孔重叠的导电组件。这允许生成2D via checker数据,即3D相邻层的组合。 2D通孔检查器数据包括矩形几何形状,这些几何形状表示与冗余通孔重叠的导电组件的每个实例。因此,输出了2D过孔检查数据,并且2D过孔检查数据中缺乏矩形几何形状提供了IC设计中没有冗余过孔的位置的数据。
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