A wireless communications apparatus includes first/second data source/sinks that respectively source/sink PDCP SDU and MAC PDU for transfer to/from a memory unit and hardware accelerators controlled by a control processor (CP). In response to sourcing transmit PDCP SDU for transfer to the memory unit, the CP controls the hardware accelerators to generate and write PDCP, RLC, MAC headers to the memory unit and assemble the generated headers and the transmit PDCP SDU from the memory unit into transmit MAC PDU for provision to the second data sink. In response to sourcing receive MAC PDU for transfer to the memory unit, the CP controls the hardware accelerators to decode PDCP, RLC MAC headers of the receive MAC PDU in the memory unit to determine locations of receive PDCP SDU in the memory unit and fetch the receive PDCP SDU from the determined locations for provision to the first data sink.
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