Vertical Tunnel FET with Self-Aligned Heterojunction

摘要

Techniques for integrating a self-aligned heterojunction for TFETs in a vertical GAA architecture are provided. In one aspect, a method of forming a vertical TFET device includes: forming a doped SiGe layer on a Si substrate; forming fins that extend through the doped SiGe layer and partway into the Si substrate such that each of the fins includes a doped SiGe portion disposed on a Si portion with a heterojunction therebetween, wherein the SiGe portion is a source and the Si portion is a channel; selectively forming oxide spacers, aligned with the heterojunction, along opposite sidewalls of only the doped SiGe portion; and forming a gate stack around the Si portion and doped SiGe that is self-aligned with the heterojunction. A vertical TFET device formed by the method is also provided.