首页> 外国专利> TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A LATE MANUFACTURING STAGE

TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A LATE MANUFACTURING STAGE

机译:在后期制造阶段绘制晶体管元件有效区域的技术

摘要

When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.
机译:当图案化用于复杂半导体器件的有源区域时,可以在后期制造阶段中执行先前沿第一横向方向图案化的有源半导体区域的切割以获得细长的半导体线。即,可以在对至少一部分栅电极结构进行图案化之后执行切割,从而实现自对准的图案化方案并且还有助于减小应变损失。

著录项

  • 公开/公告号US2019027400A1

    专利类型

  • 公开/公告日2019-01-24

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201715652585

  • 发明设计人 RYAN SPORER;GEORGE MULFINGER;

    申请日2017-07-18

  • 分类号H01L21/762;H01L21/8234;H01L21/84;H01L21/308;H01L29/06;

  • 国家 US

  • 入库时间 2022-08-21 12:05:45

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号