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High Density, Tight Array Copper Pillar Interconnect Method and Package

机译:高密度紧密阵列铜柱互连方法和封装

摘要

A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
机译:半导体器件组件和形成半导体器件组件的方法,该半导体器件组件包括第一基板,设置在第一基板上方的第二基板,基板之间的至少一个互连以及从第一基板的底表面延伸的至少一个支柱。柱电连接到互连并且位于第一基板的一侧附近。通过用导电材料填充穿过基板的通孔来形成柱。第一基板可以包括从底表面延伸到与基板的一侧相邻的柱的阵列,该柱的阵列由多个填充的通孔形成。衬底可以包括位于底表面上或位于顶表面上的测试垫。柱可以包括可移除的涂层,其使得能够在不损坏柱的内部导电部分的情况下探测柱。

著录项

  • 公开/公告号US2019172725A1

    专利类型

  • 公开/公告日2019-06-06

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号US201715830839

  • 发明设计人 OWEN R. FAY;AKSHAY N. SINGH;KYLE K. KIRBY;

    申请日2017-12-04

  • 分类号H01L21/48;H01L21/66;H01L23/498;H01L25/065;

  • 国家 US

  • 入库时间 2022-08-21 12:05:28

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