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METHOD OF MINIATURIZED CHIP ON CHIP INTERCONNECTION OF A 3D ELECTRONIC MODULE
METHOD OF MINIATURIZED CHIP ON CHIP INTERCONNECTION OF A 3D ELECTRONIC MODULE
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机译:在3D电子模块的芯片互连上最小化芯片的方法
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摘要
A 3D electronic module including, in a direction referred to as the vertical direction, a stack of electronic dice, each die including at least one chip provided with interconnect pads, this stack being attached to an interconnect circuit for the module provided with connection bumps, the pads of each chip being connected by electrical bonding wires to vertical buses that are themselves electrically linked to the interconnect circuit for the module, a bonding wire and the vertical bus to which it is linked forming an electrical conductor between a pad of a chip and the interconnect circuit, wherein each electrical bonding wire is linked to its vertical bus by forming, in a vertical plane, an oblique angle and in that the length of the bonding wire between a pad of a chip of one die and the corresponding vertical bus is different than the length of the bonding wire between one and the same pad of a chip of another die and the corresponding vertical bus, and this is obtained by wiring the bonding wire in a non-rectilinear manner to compensate for the difference in vertical length of the vertical bus from one die to the other, such that the electrical conductor between the pad of a chip of one die and the interconnect circuit, and the electrical conductor between the same pad of a chip of the other die and the interconnect circuit, are the same length.
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