首页> 外国专利> Electronic latch, a method for an electronic latch, a frequency division by two and a 4-phase generator

Electronic latch, a method for an electronic latch, a frequency division by two and a 4-phase generator

机译:电子锁存器,一种用于电子锁存器的方法,二分频和一个四相发生器

摘要

The present invention relates to an electronic latch circuit, a method, and a 4-phase generator. The electronic latch circuit comprises an output circuit comprising an output X, and an output Y. The electronic latch circuit further comprises an input circuit, comprising an input A, an input B, and a clock signal input. The input circuit is connected to the output circuit, and configured to select a state of the output circuit from the group of a first state, a second state, and a third state. The input circuit is further configured to select the first state upon detecting a high state on the input B, a transition on the clock signal input from a low state to a high state, and a low state on the input A, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state; The input circuit is further configured to select the third state upon detecting a high state on the input A, a transition on the clock signal input from a low state to a high state, and a low state on the input B, and that the electronic latch circuit is in the second state. The input circuit is further configured to select the second state upon detecting a high state on the input A, a low state on the input B, a low state on the clock signal input, and that the electronic latch circuit is in the first state.
机译:电子锁存电路,方法和四相发电机技术领域本发明涉及电子锁存电路,方法和四相发电机。电子锁存电路包括输出电路,该输出电路包括输出X和输出Y。电子锁存电路还包括输入电路,该输入电路包括输入A,输入B和时钟信号输入。输入电路连接到输出电路,并且被配置为从第一状态,第二状态和第三状态的组中选择输出电路的状态。输入电路还被配置为在检测到输入B上的高状态,在从低状态到高状态的时钟信号输入上的转变以及在输入A上的低状态时选择第一状态。锁存电路处于第二状态。输入电路还被配置为在检测到输入A的高状态,输入B的低状态,时钟信号输入的低状态以及电子锁存电路处于第一状态时选择第二状态。输入电路还被配置为在检测到输入A上的高状态,输入信号从低状态到高状态的时钟信号的转变以及输入B上的低状态时选择第三状态。锁存电路处于第二状态。输入电路还被配置为在检测到输入A的高状态,输入B的低状态,时钟信号输入的低状态以及电子锁存电路处于第一状态时选择第二状态。

著录项

  • 公开/公告号US10177748B2

    专利类型

  • 公开/公告日2019-01-08

    原文格式PDF

  • 申请/专利权人 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL);

    申请/专利号US201415524375

  • 发明设计人 REZA BAGGER;

    申请日2014-12-02

  • 分类号H03K3/35;H03K3/356;H03K3/37;H03K19/20;

  • 国家 US

  • 入库时间 2022-08-21 12:04:16

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号