A novel method of optimizing latch comparators

摘要

A new method of improving speed of latch-type comparators with preamplifier is presented .It investigates the relationship of current and transistor scales which affect delay time ( tp) in latch.It applies a mathematical model to optimize latch design .A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time .In order to suppress offset of latch , the cross-coupled loading , adopted in telescope preamplifier , which enhances the gain , is well analyzed and designed .The chip is fabricated in 0 .18μm CMOS technology .The delay time of latch comparator is less than 400 ps @500 MHz.The offset of comparator is estimated through Monte Carlo simula-tion.And power consumption is only 144 W under 1.8 V power supply .Results of on wafer testing are presented at the end of the paper .The chip occupies an area of 0.66 ×0.55 mm2 and drains current of 80μA.