Digital integrator with the sampling error compensation

摘要

digital integrator with sampling error compensation for digital signal processing in the electric systems, integrated circuits, systems, and computer programowalnych platforms containing much functions sumatora signals, system delays the signal stop multiply u017cnika signalssystem implementing mathematical functions and systems having functionality of is characterized by the fact that has 2 entry (entry 1 and entrance 2), dwuweju015bciowy mnou017cu0105cy system (19), dwuweju015bciowy sumuju0105cy system (21), a delay (23), wspu00f3u0142czyn designating system nik, hi, (26) and exit (exit 1), which is the exit (22) dwuweju015bciowego sumuju0105cego system (21).one entry is output (24) of the system (23), which delays the entry exit (22) dwuweju015bciowego sumuju0105cego system (21), the second entrance system (21) is output (20) of dwuweju015bciowego system mnou017cu0105cego (19) whose one entrance (18)'s entrance (in eju015bcie 1)that is given as a signal containing information about the numerical values corresponding to the time signal and time values, and the second entrance (25) is a way of designating system coefficient hi (26), which implements system function mathematically. isanu0105 by equation h = oi - + 1, where oi is a numerical value given for entry (entry 2).which is the entry system (26), in the form of a signal containing information about the error numerical value oi and sampling times corresponding to the time values.